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1. In the previous article, the GM / ID design method is recorded, and the parameter curve is simulated using Cadence Virtuoso IC617, you can click on the link below. This article records that the GM / ID design method mentioned in the previous article is designed to design an active load differential pair (commonly known as five-tube OTA).
2. Virtuoso Composer product. Under Manuals, there are the Virtuoso Schematic Editor Tutorial and the Virtuoso Schematic Editor User Guide that you may find helpful. The Virtuoso Schematic Composer is used to create the schematic of your design. In the schematic, it will contain devices (transistors) connected together with nets (wire.

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Designed with Cadence Virtuoso IC617 combined with GM / ID method to design active load differential pairs (five tube OTA)

Cadence Virtuoso Setup Guide. A step-by-step guide for ECE 331 students to setup Cadence Virtuoso for digital gate design. Cadence runs from a server on a UNIX/Linux platform but can be accessed from a PC using software that logs you into a UNIX server and routes monitor data to the PC. All the software you need is installed in the DECS PC labs.

tags: Cadence Virtuoso IChardwarechipsimulation

This article is my own study notes, the second article of the Cadence Virtuoso series, is also an article of introduction, and the software version is Cadence Virtuoso IC617. Other articles, please click above, see the contents of the Cadence Virtuoso column I made.

In the previous article, the GM / ID design method is recorded, and the parameter curve is simulated using Cadence Virtuoso IC617, you can click on the link below. This article records that the GM / ID design method mentioned in the previous article is designed to design an active load differential pair (commonly known as five-tube OTA).

Circuit topology

Change the circuit topology, let P-MOS become input tubes, reduce input common mode levels, and reduce noise. At the same time, in order to simplify the design, the original M5 is used instead of using an ideal current source. Note that the B end of the P-MOS is connected to the S-terminal. The final size will be larger, where Multiplier = 4 is set.

Parameter index

Examples with an example, the topic requirements are as follows:

Determine M1 and M2 size

GM1 and GM2 can be obtained from the GBW formula mentioned earlier.

G B W = A V f T = g m 1 , 2 2 π C L ⇓ g m 1 , 2 = 6.28 m A / V GBW=A_Vf_T={ g_{m1,2} over 2 pi C_L } dArr g_{m1,2}=6.28 enspace mA/V GBW=AV​fT​=2πCL​gm1,2​​⇓gm1,2​=6.28mA/V

Folding gain and bandwidth and takes GM / ID = 12.

g m I D = 12 ⇓ I D = 0.523 m A {g_m over I_D} =12 dArr I_D=0.523 enspace mA ID​gm​​=12⇓ID​=0.523mA

At the same time, the current of the branch is determined, and the ISS is twice the branch current.

Select L = 200 nm, check the curve, get the value of ID / W is 19.455.

You can get the W in M1 and M2.

I D W p 1 , 2 = 19.455 ⇓ W p 1 , 2 = 26.88 μ m { I_D over W_{p1,2}} =19.455 dArr W_{p1,2}=26.88 enspace mu m Wp1,2​ID​​=19.455⇓Wp1,2​=26.88μm

Determine M3 and M4 size

The front has been obtained from 0.523mA, and after determining the GM / ID, it can be directly calculated for W.

Here is to make it easier, GM / ID = 12. Choose L = 200 nm, check the curve, get the value of ID / W is 63.3342.

You can get the W in M3 and M4.

I D W n 3 , 4 = 63.3342 ⇓ W p 1 , 2 = 8.26 μ m { I_D over W_{n3,4}} =63.3342 dArr W_{p1,2}=8.26 enspace mu m Wn3,4​ID​​=63.3342⇓Wp1,2​=8.26μm

Parameter summary

According to the above results, the summary is the next table.

Drawing device

The schematic diagram of the inside of the device in Cadence Virtuoso IC617. Among them, in order to facilitate modification, the three key parameters of W, L, Multiplier are set to variables. Since the previous article records the detailed process, a stroke here.

Generate devices

Since the previous article records the detailed process, a stroke here.

Drawing test schematic

Since the previous article records the detailed process, a stroke here. The differential mode input here, can be used according to the previous use of VSIN, and the AC MAGNITUDE parameter in the current use of VDC is now available.

Simulation settings

Sequentially set the simulation type, select AC emulation, frequency from 1 to 1000m (like the X-axis is non-linear, more intuitive), and the specific setting of the output point is simpler, slightly. The code to output DB20 parameters is recorded as follows.

Test Results

Point green icons start simulation, come out and simulate results. The GBW was obtained from 49.2 MHz, which is basically in line with the required parameters. Of course, this circuit also has many optimized places, but this article only discusses the design, the optimized part is limited to the space, not discussed here.

Observe the DC parameters of the device, see if the preset is close. Click the device Press e to enter the next schematic, open the DC point display.

It can be seen that the values ​​of GM and ID are close to the previously expected value.

Note that the W parameters used in front simulation N-MOS and P-MOS ID / W curves are my prior computation, because different W, ID / W is slightly different, which will result in eventually calculation W has a difference in about 0.1 to 0.2um.

In actual design, we should re-simulate the ID / W curve by calculating the wiring, and then re-simulate the ID / W curve, use this new ID / W value, recalculate W, get The result is more accurate.

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Designed with Cadence Virtuoso IC617 combined with GM / ID method to design active load differential pairs (five tube OTA)

tags: Cadence Virtuoso IChardwarechipsimulation

This article is my own study notes, the second article of the Cadence Virtuoso series, is also an article of introduction, and the software version is Cadence Virtuoso IC617. Other articles, please click above, see the contents of the Cadence Virtuoso column I made.

In the previous article, the GM / ID design method is recorded, and the parameter curve is simulated using Cadence Virtuoso IC617, you can click on the link below. This article records that the GM / ID design method mentioned in the previous article is designed to design an active load differential pair (commonly known as five-tube OTA).

Circuit topology

Change the circuit topology, let P-MOS become input tubes, reduce input common mode levels, and reduce noise. At the same time, in order to simplify the design, the original M5 is used instead of using an ideal current source. Note that the B end of the P-MOS is connected to the S-terminal. The final size will be larger, where Multiplier = 4 is set.

Parameter index

Examples with an example, the topic requirements are as follows:

Determine M1 and M2 size

GM1 and GM2 can be obtained from the GBW formula mentioned earlier.

G B W = A V f T = g m 1 , 2 2 π C L ⇓ g m 1 , 2 = 6.28 m A / V GBW=A_Vf_T={ g_{m1,2} over 2 pi C_L } dArr g_{m1,2}=6.28 enspace mA/V GBW=AV​fT​=2πCL​gm1,2​​⇓gm1,2​=6.28mA/V

Folding gain and bandwidth and takes GM / ID = 12.

g m I D = 12 ⇓ I D = 0.523 m A {g_m over I_D} =12 dArr I_D=0.523 enspace mA ID​gm​​=12⇓ID​=0.523mA

At the same time, the current of the branch is determined, and the ISS is twice the branch current.

Select L = 200 nm, check the curve, get the value of ID / W is 19.455.

You can get the W in M1 and M2.

I D W p 1 , 2 = 19.455 ⇓ W p 1 , 2 = 26.88 μ m { I_D over W_{p1,2}} =19.455 dArr W_{p1,2}=26.88 enspace mu m Wp1,2​ID​​=19.455⇓Wp1,2​=26.88μm

Determine M3 and M4 size

The front has been obtained from 0.523mA, and after determining the GM / ID, it can be directly calculated for W.

Here is to make it easier, GM / ID = 12. Choose L = 200 nm, check the curve, get the value of ID / W is 63.3342.

You can get the W in M3 and M4.

I D W n 3 , 4 = 63.3342 ⇓ W p 1 , 2 = 8.26 μ m { I_D over W_{n3,4}} =63.3342 dArr W_{p1,2}=8.26 enspace mu m Wn3,4​ID​​=63.3342⇓Wp1,2​=8.26μm

Parameter summary

According to the above results, the summary is the next table.

Drawing device

The schematic diagram of the inside of the device in Cadence Virtuoso IC617. Among them, in order to facilitate modification, the three key parameters of W, L, Multiplier are set to variables. Since the previous article records the detailed process, a stroke here.

Generate devices

Since the previous article records the detailed process, a stroke here.

Drawing test schematic

Since the previous article records the detailed process, a stroke here. The differential mode input here, can be used according to the previous use of VSIN, and the AC MAGNITUDE parameter in the current use of VDC is now available.

Simulation settings

Sequentially set the simulation type, select AC emulation, frequency from 1 to 1000m (like the X-axis is non-linear, more intuitive), and the specific setting of the output point is simpler, slightly. The code to output DB20 parameters is recorded as follows.

Test Results

Point green icons start simulation, come out and simulate results. The GBW was obtained from 49.2 MHz, which is basically in line with the required parameters. Of course, this circuit also has many optimized places, but this article only discusses the design, the optimized part is limited to the space, not discussed here.

Observe the DC parameters of the device, see if the preset is close. Click the device Press e to enter the next schematic, open the DC point display.

It can be seen that the values ​​of GM and ID are close to the previously expected value.

Note that the W parameters used in front simulation N-MOS and P-MOS ID / W curves are my prior computation, because different W, ID / W is slightly different, which will result in eventually calculation W has a difference in about 0.1 to 0.2um.

In actual design, we should re-simulate the ID / W curve by calculating the wiring, and then re-simulate the ID / W curve, use this new ID / W value, recalculate W, get The result is more accurate.

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problem m i n X g ( X ) = 1 2 X T G X + X T C mathop{min}limits_{X}g(X) = frac{1}{2}X^TGX+X^TC Xmin​g(X)=21​XTGX+XTC s.t. a i T X = b i , i ∈ E a_i^TX = b_i,iin E aiT​X=bi​,i∈E a i T X &...

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